In the case of semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory), and RAM devices (RAM=Random Access Memory or read write memory).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address again later.
The corresponding address can be input into the RAM device via address pins or address input pins, respectively. For the input and the output of the data, a plurality of e.g., 16, data pins or data input/output pins (I/Os or inputs/outputs) are provided. By applying an appropriate signal (e.g., a read/write signal) at a write/read selection pin there may be selected whether data are to be stored or to be read out (at the moment).
Since as many memory cells as possible are to be accommodated in a RAM device, one has been trying to realize them as simple as possible. In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist, e.g., of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitor with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a short time only. Therefore, a “refresh” must be performed regularly, e.g., approximately every 64 ms.
For technological reasons, the individual memory cells are, in the case of memory devices, in particular DRAM devices, arranged side by side in a plurality of rows and columns in a rectangular matrix (that is regularly subdivided into a plurality of cell fields) or a rectangular array (that is regularly subdivided into a plurality of cell fields), respectively.
In order to achieve a correspondingly high overall storage capacity and/or a data read or write rate that is as high as possible, instead of one single array, a plurality of, e.g., four—substantially rectangular—individual arrays may be provided in an individual RAM device or chip (e.g., a multi-bank chip) ( “memory banks”).
To perform a write or read access, a particular, predetermined sequence of commands has to be run through:
By means of a word line activate command (activate command (ACT)), a corresponding word line—that is, in particular, assigned to a particular array—(and that is defined by the row address (“row address”) is, for instance, activated first of all.
This results in that the data values stored in the memory cells that are assigned to the corresponding word line are read out by the sense amplifiers that are assigned to the corresponding word line (“activated state” of the word line).
Subsequently—by means of a corresponding read or write command (Read (RD) or Write (WT) command)—it is initiated that the corresponding data—that are then exactly specified by the corresponding column address (“column address”)—are correspondingly output by the corresponding sense amplifier(s) that is/are assigned to the bit line specified by the column address (“column address”) (or—vice versa—the data are read into the corresponding memory cells).
Next—by means of a word line deactivate command (e.g., a precharge command (PRE command))—the corresponding word line is deactivated again, and the corresponding array is prepared for the next word line activate command (activate command (ACT)).
The above-mentioned sense amplifiers are each arranged in a sense amplifier region positioned between two cell fields, wherein—for reasons of space—one and the same sense amplifier may be assigned to two different cell fields (namely to the two cell fields that are directly adjacent to the corresponding sense amplifier region) (“shared sense amplifier”).
Depending on whether data are to be read out from the cell field positioned at the left or at the right next to the respective sense amplifier (or from the cell field positioned above or below the respective sense amplifier), the corresponding sense amplifier is switched to the corresponding cell field (in particular to the corresponding bit line assigned to the respective cell field) by means of appropriate switches (or is electrically connected with the corresponding cell field, in particular the corresponding bit line assigned to the respective cell field), or switched off the corresponding cell field (or the corresponding bit line assigned to the respective cell field) (or electrically disconnected from the corresponding cell field (or the corresponding bit line assigned to the respective cell field)).
The threshold voltages (Vth) of transistors, in particular of field effect transistors—and thus also the threshold voltages of field effect transistors used in sense amplifiers—are temperature-dependent.
In the case of field effect transistors with a relatively low threshold voltage (Vth), the range of the threshold voltage may be in the same magnitude as the threshold voltage itself.
The threshold voltage (Vth) determines—substantially—the behavior of a field effect transistor in a circuit. One reason therefor is, for instance, that field effect transistors often are to be operated in the activated region in which the gate source voltage (Vgs) has to be higher than the threshold voltage (Vth), or often also in the saturation region (wherein the drain source voltage (Vds) has to be higher than the saturation voltage (Vdsat, with Vdsat=Vgs−Vth).
It would therefore be desirable if the threshold voltage (Vth) were—other than indicated above—temperature-independent or largely temperature-independent.
In particular circuits, especially, e.g., in field effect transistors used in the above-mentioned sense amplifiers, there occurs the problem that it has to be ensured that the respective transistor threshold voltage (Vth) does not fall below a minimum value even at relatively high temperatures (e.g., to avoid the occurrence of leaking currents). This entails the risk that—vice versa—in the case of relatively low temperatures the threshold voltage (Vth) becomes so high that the operability of the respective circuit is no longer guaranteed.
For these and other reasons, there is a need for the present invention.